This invention relates to programmable logic array (PLA) integrated circuits, and more particularly to a PLA integrated circuit that uses a multiplexer interconnect architecture.
As shown by commonly-assigned U.S. Pat. No. 4,871,930 (Wong), which is hereby incorporated by reference in its entirety, and the references cited therein, programmable logic devices (PLDs) are well known integrated circuits. As described in Wong, a major obstacle in increasing the logic density in previously known PLDs was the size of the single global interconnection array which increased as the square of the number of output functions. This obstacle was overcome to a large extent by the use of a programmable interconnect array (PIA) disclosed in Wong. In a PLD using a PIA, a single global interconnection array using erasable programmable read-only memory (EPROM) cells was used to route signals to and from logic array blocks (LABS) which contained logic elements, logic modules, and a local interconnection array.
The architecture using PIAs and LABs disclosed in Wong produced a generation of successful PLDs available commercially from Altera Corporation of San Jose, Calif. Yet, to meet ever increasing technological demands, PLDs have been constantly increasing in both size and complexity. In particular, to achieve higher logic density, more logic elements have been incorporated into PLDs and this has necessitated increasing the size of the PIA. However, a significant amount of the power used in PLDs is consumed in the programmable elements of the PIA, and a speed limitation is capacitive loading in the programmable elements of the PIA. Increasing the size of the PIA, therefore, leads undesirably to higher power consumption and reduction in speed.
An enhancement to the PIA was disclosed in a commonly-assigned U.S. Pat. No. 5,241,224, that successfully addressed the above problems associated with increased chip density. It was realized that, as the complexity of PLDs increases, the increase in the number of programmable elements in the PIA is responsible for a significant increase in the amount of the power consumed, and is responsible for a significant decrease in the speed due to the capacitive loading of EPROM cells. Furthermore, it was observed that only a small fraction of the total number of EPROM cells in the PIA is used, so that most of the increased capacitive loading and power consumption is unnecessary.
Accordingly, in the enhanced PIA architecture, the programmable elements and thus their associated power consumption and capacitive loading were eliminated by an alternative global interconnect array (GIA) architecture. In the GIA, selected global conductors are connected to the inputs of a group of multiplexers in a predetermined pattern, and the outputs of the multiplexers are connected to the inputs of logic modules in the LABS. Programmability through the use of a global EPROM in the PIA of the prior PLDs is replaced by programmability of the multiplexers connected to the GIA. The multiplexers are controlled by an array of programmable architecture bits so that the signals on selected global conductors can be routed to the inputs of selected logic modules.
Commonly assigned U.S. Pat. No. 5,444,391 discloses a PLD circuit which combines the high performance global interconnect array (GIA) architecture with logic array blocks (LABs) that use zero-power CMOS logic modules. The CMOS logic module includes a multi-input look-up table and a flip-flop type device for implementing the logic. The GIA employs a very fast multiplexer-based interconnect network to carry all signals that must span across LAB boundaries, as well as all input signals into the device.
Commonly assigned U.S. patent application Ser. No. 60/028,206 shows an architecture using "folded rows." A row of LABs is folded back along a second side of an interconnect region, giving LABs on both sides of the interconnect region. Connecting lines thus extend in both directions from the global conductors in the interconnect region to the LABs. This architecture allows for a higher density of logic, and provides logic regions with more uniform horizontal and vertical characteristics. However, an increased number of connections are required in the interconnect region, requiring more transistor switches in this region, impacting the interconnect region layout and loading the global conductors.